1. Field of the Invention
The present invention relates to bidirectional input/output buffers which are capable of simultaneously transmitting data in two directions through one transmission line, and more particularly, to a bidirectional input/output buffer that operates in current mode.
2. Description of the Related Art
Improvements in the performance of high-speed integrated circuits have been limited by data transmission speeds between chips. In high-speed data communications, bidirectional input/output system, which can transmit data in both directions through a single cable, are advantageous because data input and output can be performed simultaneously using only one pin in a system having a limited number usable pins. A bidirectional input/output buffer restores a data input signal from mixed input/output signals. The speed of a bidirectional buffer is typically limited by the speed of the restoring circuit.
FIG. 1 is a schematic diagram illustrating the construction of a conventional bidirectional input/output buffer. As shown in FIG. 1, a conventional bidirectional input/output buffer includes a voltage signal terminal IN1, an output terminal OUT1, a receiving terminal RE1, a reference voltage generator 103A, an output buffer 101A, and a voltage comparator 102A.
In operation, an output data signal, which is to be transmitted to an external device, is applied to terminal IN1. The restored value of a signal received from an external device appears at terminal RE1. Reference voltage generator 103A generates a reference voltage Vref1 according to the logic value of signal applied to terminal IN1. The voltage comparator 102A restores the signal received from an external device by comparing the voltage of the output terminal OUT1, which carries a mixed signal which is a combination of the signal to be transmitted to an external device and the signal received from the external device, with the reference voltage Vref1.
The operation of the buffer of FIG. 1 will now be described in more detail. The voltage at the output terminal OUT1 is a composite voltage which corresponds to the average value of the voltages of the signals transmitted by two chips 100A and 100B. Assuming that there are two voltage values 0 V and Vh representing two logic values that can be transmitted between the two chips 100A and 100B, the voltage at the output terminal OUT1 can be either Vh, 0.5.times.Vh, or 0 V. That is, if both of the voltage signals at terminals IN1 and IN2 are at logic "HIGH" levels, the voltage at output terminal OUT1 is Vh; if only one of the voltage signal at terminals IN1 and IN2 are "HIGH", the voltage at output terminal OUT1 is 0.5.times.Vh; and if both of the voltage signal terminals IN1 and IN2 are at logic "LOW" levels, OUT1 is at 0 V. Therefore, a restored voltage signal is generated at the receiving terminal RE1 by comparing the reference voltage Vref1, which is selected according to the voltage signal .phi.IN1, with the voltage of the output terminal OUT1.
The following Table 1 shows the values of the restored signals RE1 and RE2, the values of the reference voltages Vref1 and Vref2, and the values of the signals OUT1 and OUT2 for various combinations of .phi.IN1 and .phi.IN2.
TABLE 1 ______________________________________ .phi.IN1 "0" (LOW) "0" (LOW) "1" (HIGH) "1" (HIGH) .phi.IN2 "0" (LOW) "1" (HIGH) "0" (LOW) "1" (HIGH) Vref1 0.25 .times. Vh 0.25Vh 0.75 .times. Vh 0.75 .times. Vh Vref2 0.25 .times. Vh 0.75 .times. Vh 0.25 .times. Vh 0.75 .times. Vh OUT1 0 0.5 .times. Vh 0.5 .times. Vh Vh (=OUT2) restored signal "0" (LOW) "1" (HIGH) "0" (LOW) "1" (HIGH) (RE1) restored signal "0" (LOW) "0" (LOW) "1" (HIGH) "1" (HIGH) (RE2) ______________________________________
A problem with the conventional bidirectional input/output buffer of FIG. 1 is that it does not achieve adequate operating speeds to support improved high-speed data communications. Accordingly, a need remains for a faster bidirectional input/output buffer.